1. Field of the Invention
The present invention relates generally to systems and methods for generating clock signals. In particular, the present invention relates to a system and a method for generating clock signals of different frequencies using a tunable digital oscillator circuit. Still more particularly, the present invention relates to a tunable oscillator circuit formed exclusively from digital logic circuits.
2. Description of the Background Art
Oscillators are well known in the prior art for producing clock signals. Most conventional oscillators require some form of R-C network or resistor-capacitor combination. Such R-C networks are typically used in combination with a crystal to produce a well-defined, stable square wave output. However, one problem with such existing clock generators or oscillators is that they are difficult and expensive to include as part of an integrated circuit because of the required analog components. It is often very difficult, if not impossible, to make usable resistors and capacitors on integrated circuits, especially for certain design processes. Furthermore, the addition of such analog components to integrated circuits consumes much of the power and layout area of the integrated circuit, thereby reducing the overall amount of circuitry that can be put on one integrated circuit and increasing the cost of the die. Thus, there is a need for a system and method for producing a clock signal that does not require the conventional resistor-capacitor combinations.
Modern integrated circuits often need not just one clock signal but several clock signals of differing frequencies. One common approach is to use a phase lock loop (PLL) circuit to provide a programmable frequency output. While PLL circuits provide very precise frequency output, they create a number of problems when included as part of an integrated circuit. First, programmable oscillators constructed using PLL circuits, while very good for many applications, are very sensitive to process technologies and must often be redesigned as process technologies change. This is a particular problem for integrated circuits where the process technologies are constantly migrating to smaller sizes such as the transition from 0.35 to 0.25 micron technologies. Therefore, each time the process technology changes the programmable oscillators must be redesigned. Second, they are expensive due to the components external to the chip, such as resistors, capacitors and crystals, required to make the design work. Third, the PLL circuits consume large amounts of power and significantly increase the gate count and area consumed. Thus, there is need for a square wave digital oscillator that does not require the use of a PLL circuit.
With the advent of portable computers, power consumption has become a key focus due to the fact that batteries are able to provide only discrete and limited amounts of power. This desire to preserve power for portable computing has mandated reduced power consumption for integrated circuits. One technique used to save power is to switch clocks off when they are not needed and back the need arises. Thus, there is a need for a square wave digital oscillator that can be switched "on" and "off" very quickly. Such an oscillator would allow sub-systems of portable computers to be switched into low power mode when the sub-systems including the main system clocks are switched off. Thus, there is need for a tunable digital oscillator that can be switched on and off quickly (on within nanoseconds and off within two clock cycles). Furthermore, the switching of the tunable digital oscillator between the on and off state must be glitch or error free.
Therefore, there is a need for a square wave digital oscillator on an integrated circuit that can be tuned over a wide frequency range using standard, off the shelf, digital logic components.